The present invention relates generally to a method and apparatus for simulating digital circuits. In particular, the present invention relates to a method for rapidly modeling and statistically analyzing digital circuits to detect signal timing problems.
Digital circuit simulators have been known for many years, and are typically used to test new circuit designs without physically building expensive prototypes. One major purpose of this testing is to ensure that during real-time operation there will not be any signal timing conflicts that might cause the circuit to operate improperly. Such timing conflicts can result in undesired pulses and logic values as a consequence of circuit elements receiving information in an inappropriate order. For example, a digital latch must receive the data state before the latch signal. The amount of time that the data must be stable prior to the latch signal is called setup time. If a data signal violates the setup time (i.e. there is a data signal transition too close to the latch signal), the output of the latch may be set to an incorrect value.
Many digital simulation methods focus on modeling delay time in signal propagation through components. The simplest simulation method is known as fixed delay modeling. This method models each component with a predetermined, fixed delay. Real components, however, have propagation delays that vary considerably due to transistor variations, differences in circuit operation, temperature, supply voltage, etc. For this reason fixed delay modeling detects only a small fraction of the potential signal conflicts.
Two different approaches have been developed in response to the inadequacies of fixed delay modeling. These are commonly known as Monte Carlo and Min/Max simulators. Monte Carlo simulators perform repetitive fixed delay analyses, with each analysis using delay parameters randomly selected according to a distribution describing the variation in component delays. The results from each analysis are retained and combined together to form the distribution of delay through the network. When the analyses have all been completed, the output provides a more comprehensive list of conflicts than provided by simple fixed delay modeling. Also, the ratio of the number of occurrences of a particular error to the total number of analyses provides a probability for the occurrence of the error. Because of the randomized selection process, however, Monte Carlo analysis has the significant drawback that a great many analyses must be performed to achieve statistically significant results, requiring a great deal of time for the complete simulation.
As its name implies, the Min/Max method represents delay and signal transition ranges by their minimum and maximum values. Min/Max simulations, like fixed delay simulations, are determinate simulators requiring but a single simulation pass, and are therefore much faster than Monte Carlo simulations. Unfortunately, the results of a Min/Max simulation represent extended extremes. This type of analysis can only identify the potential duration of a signal conflict, which is essentially unrelated to its likelihood of occurrence, and therefore of limited usefulness in ranking problems to be addressed. Min/Max simulations thus report a large number of potential errors that realistically have only an infinitesimal likelihood of occurrence. Min/Max analysis has been augmented in order to reduce this excessive reporting of illusory errors. One augmentation is the use of reconvergent fanout analysis in conjunction with the normal Min/Max analysis. Reconvergent fanout analysis accounts for some of the potential correlation between different logic signals, and improves accuracy. However, Min/Max analysis is still not very satisfactory.
What is needed is a fast, determinate, single pass digital circuit simulator that can accurately determine probability ratings for signal conflicts.